A low-voltage and energy-efficient full adder cell based on carbon nanotube technology

Keivan Navi; Rabe'e Sharifi Rad; Mohammad Hossein Moaiyeri; Amir Momeni

doi:10.1007/BF03353628

Issue

Vol. 2 No. 2 (2010)

Issue Published : Apr 1, 2010

A low-voltage and energy-efficient full adder cell based on carbon nanotube technology

https://doi.org/10.1007/BF03353628

Keivan Navi

Faculty of Electrical and Computer Engineering, Shahid Beheshti University, GC, Tehran, Iran

Rabe'e Sharifi Rad

Faculty of Electrical and Computer Engineering, Shahid Beheshti University, GC, Tehran, Iran

Mohammad Hossein Moaiyeri

Faculty of Electrical and Computer Engineering, Shahid Beheshti University, GC, Tehran, Iran

Amir Momeni

Faculty of Electrical and Computer Engineering, Shahid Beheshti University, GC, Tehran, Iran

Corresponding Author: Keivan Navi

navi@sbu.ac.ir

Nano-Micro Letters, Vol. 2 No. 2 (2010), Article Number: 114-120
Article Published : Jun 30, 2010

Abstract

Scaling problems and limitations of conventional silicon transistors have led the designers to exploit novel nano-technologies. One of the most promising and feasible nano-technologies is CNT (Carbon Nanotube) based transistors. In this paper, a high-speed and energy-efficient CNFET (Carbon Nanotube Field Effect Transistor) based Full Adder cell is proposed for nanotechnology. This design is simulated in various supply voltages, frequencies and load capacitors using HSPICE circuit simulator. Significant improvement is achieved in terms of speed and PDP (Power-Delay-Product) in comparison with other classical and state-of-the-art CMOS and CNFET-based designs, existing in the literature. The proposed Full Adder can also drive large load capacitance and works properly in low supply voltages.

Keywords

CNFET Low-Voltage Full-Adder Minority-Function Nanotechnology

Navi, Keivan, Rabe’e Sharifi Rad, Mohammad Hossein Moaiyeri, and Amir Momeni. 2010. “A Low-Voltage and Energy-Efficient Full Adder Cell Based on Carbon Nanotube Technology”. Nano-Micro Letters 2 (2):114-20. https://doi.org/10.1007/BF03353628.

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References

K. Navi, S. Sayedsalehi, R. Farazkish and M. Rahimi Azghadi, J. Comp. Theor. Nanosci. 7, 1546 (2010).doi:10.1166/jctn.2010.1517.
V. Schmidt, H. Riel, S. Senz, S. Karg, W. Riess and U. Gçsele, Small 2, 85 (2006). doi:10.1002/smll.200500181.
A. Raychowdhury and K. Roy, IEEE Transactions on Circuits and Systems 54, 2391 (2007).doi:10.1109/TCI.2007.907799.
K. Navi, A. Momeni, F. Sharifi and P. Keshavarzian, IEICE Electron. Exp. 6, 1395 (2009). doi:10.1587/elex.6.1395.
K. Navi, M. Rashtian, A. Khatir, P. Keshavarzian and O. Hashemipour, Nanoscale Res. Lett. 5, 589 (2010). doi:10.1007/s11671-010-9575-4.
A. S. Molahosseini, K. Navi, C. Dadkhah, O. Kavehei and S. Timarchi, IEEE T. Circuits Sys. I 57, 823 (2010). doi: 10.1109/TCSI.2009.2026681.
P. Keshavarzian and K. Navi, IEICE Electron. Exp. 6, 546 (2009). doi:10.1587/elex.6.546.
Raychowdhury and K. Roy, IEEE T. Nanotech. 4, 168 (2005). doi:10.1109/TNANO.2004.842068.
P. Keshavarzian and K. Navi, Int. J. Nanotech. 6, 942 (2009). doi:10.1504/IJNT.2009.027557.
M. Budnik, A. Raychowdhury, A. Bansal and K. Roy, 43rd Aannual Design Automation Conference, San Francisco, CA, USA, pp. 935 (2006).
R. Zimmermann and W. Fichtner, IEEE J. Solid-State Circuits 32, 1079 (1997). doi:10.1109/4.597298.
O. Kavehei, M. Rahimi Azghadi, K. Navi and A.P. Mirbaha, In Proc. 2008 IEEE computer Society Annual Symposium on VLSI, 10 (2008).
C. H. Chang, J. Guand and M. Zhang, IEEE Transactions on Very Large Scale Integration Systems 13, 686 (2005).
S. Goel, A. Kumar and M. A. Bayoumi, IEEE Transactions on Very Large Scale Integration Systems 14, 1309 (2006). doi:10.1109/TVLSI.2006.887807.
N. Weste and K. Eshraghian, “Principles of CMOS VLSI Design, A System Perspective”, AddisonWesley, Reading, MA, (1993).
S. Ijiima, Nature 354, 56 (1991). doi:10.1038/354056a0.
Y. Bok Kim, Y. B. Kim and F. Lombardi, In Proc. 2009 IEEE International Midwest Symposium on Circuits and Systems 1130 (2009).
S. J. Tans, R. M. Verschueren and C. Dekker, Nature 393, 49 (1998). doi:10.1038/29954.
G. Cho, Y. B. Kim and F. Lombardi, In Proc. 2009 IEEE International Instrumentation and MeasurementTechnology Conference 909 (2009).
J. Deng and H. SP Wong, IEEE T.Electron. Devices 54, 3186 (2007). doi:10.1109/TED.2007.909030.
J. Deng and H. SP Wong, IEEE T. Electron. Devices 54, 3195 (2007). doi:10.1109/TED.2007.909043.
Stanford University CNFET Model website [Online 2008]. Available: http://www.nano.stanford.edu/model.php?id=23.compat1
K. Navi, M. H. Moaiyeri, R. Faghih Mirzaee, O. Hashemipour and B. Mazloom Nezhad, “Two new low-power full adders based on majority-not gates”, Elsevier, Microelectron. J. 40, 126 (2009).
M. H. Moaiyeri, R. Faghih Mirzaee, K. Navi, T. Nikoubin and O. Kavehei, Int. J. Electron. 97, 647 (2010). doi:10.1080/00207211003646944.s

References

K. Navi, S. Sayedsalehi, R. Farazkish and M. Rahimi Azghadi, J. Comp. Theor. Nanosci. 7, 1546 (2010).doi:10.1166/jctn.2010.1517.

V. Schmidt, H. Riel, S. Senz, S. Karg, W. Riess and U. Gçsele, Small 2, 85 (2006). doi:10.1002/smll.200500181.

A. Raychowdhury and K. Roy, IEEE Transactions on Circuits and Systems 54, 2391 (2007).doi:10.1109/TCI.2007.907799.

K. Navi, A. Momeni, F. Sharifi and P. Keshavarzian, IEICE Electron. Exp. 6, 1395 (2009). doi:10.1587/elex.6.1395.

K. Navi, M. Rashtian, A. Khatir, P. Keshavarzian and O. Hashemipour, Nanoscale Res. Lett. 5, 589 (2010). doi:10.1007/s11671-010-9575-4.

A. S. Molahosseini, K. Navi, C. Dadkhah, O. Kavehei and S. Timarchi, IEEE T. Circuits Sys. I 57, 823 (2010). doi: 10.1109/TCSI.2009.2026681.

P. Keshavarzian and K. Navi, IEICE Electron. Exp. 6, 546 (2009). doi:10.1587/elex.6.546.

Raychowdhury and K. Roy, IEEE T. Nanotech. 4, 168 (2005). doi:10.1109/TNANO.2004.842068.

P. Keshavarzian and K. Navi, Int. J. Nanotech. 6, 942 (2009). doi:10.1504/IJNT.2009.027557.

M. Budnik, A. Raychowdhury, A. Bansal and K. Roy, 43rd Aannual Design Automation Conference, San Francisco, CA, USA, pp. 935 (2006).

R. Zimmermann and W. Fichtner, IEEE J. Solid-State Circuits 32, 1079 (1997). doi:10.1109/4.597298.

O. Kavehei, M. Rahimi Azghadi, K. Navi and A.P. Mirbaha, In Proc. 2008 IEEE computer Society Annual Symposium on VLSI, 10 (2008).

C. H. Chang, J. Guand and M. Zhang, IEEE Transactions on Very Large Scale Integration Systems 13, 686 (2005).

S. Goel, A. Kumar and M. A. Bayoumi, IEEE Transactions on Very Large Scale Integration Systems 14, 1309 (2006). doi:10.1109/TVLSI.2006.887807.

N. Weste and K. Eshraghian, “Principles of CMOS VLSI Design, A System Perspective”, AddisonWesley, Reading, MA, (1993).

S. Ijiima, Nature 354, 56 (1991). doi:10.1038/354056a0.

Y. Bok Kim, Y. B. Kim and F. Lombardi, In Proc. 2009 IEEE International Midwest Symposium on Circuits and Systems 1130 (2009).

S. J. Tans, R. M. Verschueren and C. Dekker, Nature 393, 49 (1998). doi:10.1038/29954.

G. Cho, Y. B. Kim and F. Lombardi, In Proc. 2009 IEEE International Instrumentation and MeasurementTechnology Conference 909 (2009).

J. Deng and H. SP Wong, IEEE T.Electron. Devices 54, 3186 (2007). doi:10.1109/TED.2007.909030.

J. Deng and H. SP Wong, IEEE T. Electron. Devices 54, 3195 (2007). doi:10.1109/TED.2007.909043.

Stanford University CNFET Model website [Online 2008]. Available: http://www.nano.stanford.edu/model.php?id=23.compat1

K. Navi, M. H. Moaiyeri, R. Faghih Mirzaee, O. Hashemipour and B. Mazloom Nezhad, “Two new low-power full adders based on majority-not gates”, Elsevier, Microelectron. J. 40, 126 (2009).

M. H. Moaiyeri, R. Faghih Mirzaee, K. Navi, T. Nikoubin and O. Kavehei, Int. J. Electron. 97, 647 (2010). doi:10.1080/00207211003646944.s

Issue

Vol. 2 No. 2 (2010)

A low-voltage and energy-efficient full adder cell based on carbon nanotube technology

Corresponding Author: Keivan Navi

Abstract

Keywords

Download Citation

References

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