Comparative Performance Evaluation of Large FPGAs with CNFET- and CMOS-based Switches in Nanoscale
Corresponding Author: Keivan Navi
Nano-Micro Letters,
Vol. 3 No. 3 (2011), Article Number: 178-188
Abstract
Routing resources are the major bottlenecks in improving the performance and power consumption of the current FPGAs. Recently reported researches have shown that carbon nanotube field effect transistors (CNFETs) have considerable potentials for improving the delay and power consumption of the modern FPGAs. In this paper, hybrid CNFET-CMOS architecture is presented for FPGAs and then this architecture is evaluated to be used in modern FPGAs. In addition, we have designed and parameterized the CNFET-based FPGA switches and calibrated them for being utilized in FPGAs at 45 nm, 22 nm and 16 nm technology nodes. Simulation results show that the CNFET-based FPGA switches improve the current FPGAs in terms of performance, power consumption and immunity to process and temperature variations. Simulation results and analyses also demonstrate that the performance of the FPGAs is improved about 30%, on average and the average and leakage power consumptions are reduced more than 6% and 98% respectively when the CNFET switches are used instead of MOSFET FPGA switches. Moreover, this technique leads to more than 20.31% smaller area. It is worth mentioning that the advantages of CNFET-based FPGAs are more considerable when the size of FPGAs grows and also when the technology node becomes smaller.
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- A. Gayasen, N. Vijaykrishnan and M. J. Irwin, IEEE 42nd annual Design Automation Conference, 921, June (2005).
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References
A. Gayasen, N. Vijaykrishnan and M. J. Irwin, IEEE 42nd annual Design Automation Conference, 921, June (2005).
G. Cho, Y. B. Kim, F. Lombardi and M. Choi, IEEE International Instrumentation and Measurement Technology Conference, 909, May (2009).
M. A. Tehrani, F. Safaei, M. H. Moaiyeri and K. Navi, Microelectron. J. 42, 913 (2011). http://dx.doi.org/10.1016/j.mejo.2011.03.004
M. H. Moaiyeri, R. F. Mirzaee, K. Navi and O. Hashemipour, Nano-Micro Lett. 3, 43 (2011). http://dx.doi.org/10.5101/nml.v3i1.p43-50
M. H. Moaiyeri, A. Doostaregan and K. Navi, IET Circ. Dev. Syst. 5, 285 (2011).
K. Navi, R. Sharifi Rad, M. H. Moaiyeri and A. Momeni, Nano-Micro Lett. 2, 114 (2010). http://dx.doi.org/10.5101/nml.v2i2.p114-120
L. K. Scheffer, IEEE 44th annual Design Automation Conference, 576, June (2007).
N. Patil, A. Lin, J. Zhang, H. P. Wong, and S. Mitra, IEEE 46th Annual Design Automation Conference, 304, July (2009).
G. F. Close and H. P. Wong, IEEE Trans. Nanotech. 7, 596 (2008). http://dx.doi.org/10.1109/TNANO.2008.927373
C. Dong, S. Chilstedt and D. Chen, ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 161, Feb. (2009).
S. Eachempati, A. Nieuwoudt, A. Gayasen, N. Vijaykrishnan and Y. Massoud, IEEE conference on Design, automation and test in Europe, 1, April 2007.
W. Zhang, N. K. Jha, and L. Shang, IEEE 43rd Annual Design Automation Conference, 711, July 2006.
M. Jamalizadeh, F. Sharifi, M. H. Moaiyeri, K. Navi and O. Hashemipour, Nano-Micro Lett. 2, 227 (2010).
K. Natori, Y. Kimura and T. Shimizu, J. Appl. Phys. 97, 034306 (2005). http://dx.doi.org/10.1063/1.1840096
Y. B. Kim, Y. B. Kim and F. Lombardi, IEEE International Midwest Symposium on Circuits and Systems, 1130, August 2009.
J. Deng, “Device modeling and circuit performance evaluation for nanoscale devices: silicon technology beyond 45 nm node and carbon nanotube field effect transistors”, Doctoral Dissertation, Stanford University, 2007.
J. Deng and H. P. Wong, IEEE Trans. Electron Dev. 54, 3186 (2007). http://dx.doi.org/10.1109/TED.2007.909030
M. S. Haque, K. B. K. Teo, N. L. Rupensinghe, S. Z. Ali, I. Haneef, S. Maeng, J. Park, F. Udrea and W. I. Milne, Nanotechnology 19, 025607 (2008). http://dx.doi.org/10.1088/0957-4484/19/02/025607
G. F. Close, S. Yasuda, B. Paul, S. Fujita and H. P. Wong, Nano Lett. 8, 706 (2008). http://dx.doi.org/10.1021/nl0730965
K. Siozios, D. Soudris and G. Economakos, IEEE 16th International conference on Digital Signal Processing, 1, July 2009.
A. Raychowdhury and K. Roy, IEEE T. Circuits Syst. 54, 2391 (2007). http://dx.doi.org/10.1109/TCSI.2007.907799
A. Javey, J. Guo, D. Farmer, Q. Wang, E. Yenilmez, R. Gordon, M. Lundstrom and H. Dai, Nano Lett. 4, 1319 (2004). http://dx.doi.org/10.1021/nl049222b
A. Javey, R. Tu, D. B. Farmer, J. Guo, R. G. Gordon and H. Dai, Nano Lett. 5, 345 (2005). http://dx.doi.org/10.1021/nl047931j
S. O. Koswatta, D. E. Nikonov and M. S. Lundstrom, IEEE 27th Proceedings of the Technology Digest International Electron Device Meeting, 518, December 2005.
X. Li, H. Yang and H. Zhong, IEEE 8th International Conference on Solid-State and Integrated Circuit Technology, 1880, October 2006.
K. K. W. Poone, S. J. E. Wilton and A. Yan, ACM Transactions on Design Automation of Electronic Systems 10, 187 (2005).
BLAC CAD Group, MCNC benchmarks, Available on http://vlsicad.cs.binghamton.edu/benchmarks.html, 2010.
J. Deng and H. P. Wong, IEEE T. Electron. Dev. 54, 3195 (2007). http://dx.doi.org/10.1109/TED.2007.909043
M. H. Moaiyeri, R. F. Mirzaee, K. Navi, T. Nikoubin and O. Kavehei, Int. J. Electro. 97, 647 (2010). http://dx.doi.org/10.1080/00207211003646944
Kuon, R. Tessier and J. Rose, Foundations and Trends in Electronic Design Automation, 2, 135 (2007). http://dx.doi.org/10.1561/1000000005