Issue

Vol. 17 (2025)

High-Performance Gate-All-Around Field Effect Transistors Based on Orderly Arrays of Catalytic Si Nanowire Channels

https://doi.org/10.1007/s40820-025-01674-8
Wei Liao
School of Electronic Science & Engineering, Nanjing University, Nanjing 210093, People’s Republic of China
Wentao Qian
School of Electronic Science & Engineering, Nanjing University, Nanjing 210093, People’s Republic of China
Junyang An
School of Electronic Science & Engineering, Nanjing University, Nanjing 210093, People’s Republic of China
Lei Liang
School of Electronic Science & Engineering, Nanjing University, Nanjing 210093, People’s Republic of China
Zhiyan Hu
School of Electronic Science & Engineering, Nanjing University, Nanjing 210093, People’s Republic of China
Junzhuan Wang
School of Electronic Science & Engineering, Nanjing University, Nanjing 210093, People’s Republic of China
Linwei Yu
School of Electronic Science & Engineering, Nanjing University, Nanjing 210093, People’s Republic of China

Corresponding Author: Linwei Yu

yulinwei@nju.edu.cn

Nano-Micro Letters, Vol. 17 (2025), Article Number: 154

Abstract

Gate-all-around field-effect transistors (GAA-FETs) represent the leading-edge channel architecture for constructing state-of-the-art high-performance FETs. Despite the advantages offered by the GAA configuration, its application to catalytic silicon nanowire (SiNW) channels, known for facile low-temperature fabrication and high yield, has faced challenges primarily due to issues with precise positioning and alignment. In exploring this promising avenue, we employed an in-plane solid–liquid-solid (IPSLS) growth technique to batch-fabricate orderly arrays of ultrathin SiNWs, with diameters of DNW = 22.4 ± 2.4 nm and interwire spacing of 90 nm. An in situ channel-releasing technique has been developed to well preserve the geometry integrity of suspended SiNW arrays. By optimizing the source/drain contacts, high-performance GAA-FET devices have been successfully fabricated, based on these catalytic SiNW channels for the first time, yielding a high on/off current ratio of 107 and a steep subthreshold swing of 66 mV dec−1, closing the performance gap between the catalytic SiNW-FETs and state-of-the-art GAA-FETs fabricated by using advanced top-down EBL and EUV lithography. These results indicate that catalytic IPSLS SiNWs can also serve as the ideal 1D channels for scalable fabrication of high-performance GAA-FETs, well suited for monolithic 3D integrations.


Highlights:
1 A high-density array of orderly silicon nanowires (SiNWs) was grown in precise locations, with diameter of DNW = 22.4 ± 2.4 nm and interwire spacing of 90 nm.
2 A special suspension-contact protocol has been developed to reliably suspend the in-plane solid-liquid-solid SiNWs to serve as ultrathin quasi-1D channels for gate-all-around field-effect transistors (GAA-FETs).
3 By optimizing the source/drain metal contacts, high-performance catalytical GAA-FETs have been successfully demonstrated, achieving a high on/off current ratio of 107 and a steep subthreshold swing of 66 mV dec-1.

Keywords

In-plane solid-liquid-solid Ultrathin silicon nanowires Gate-all-around field-effect transistors (GAA-FETs)
Liao, Wei, Wentao Qian, Junyang An, Lei Liang, Zhiyan Hu, Junzhuan Wang, and Linwei Yu. 2025. “High-Performance Gate-All-Around Field Effect Transistors Based on Orderly Arrays of Catalytic Si Nanowire Channels”. Nano-Micro Letters 17 (February):154. https://doi.org/10.1007/s40820-025-01674-8.
Download Citation
Endnote/Zotero/Mendeley (RIS)
BibTeX
References
  1. S. Bangsaruntip, G.M. Cohen, A. Majumdar, Y. Zhang, S.U. Engelmann et al., High Performance and Highly Uniform Gate-All-Around Silicon Nanowire MOSFETs with Wire Size Dependent Scaling. 2009 IEEE international electron devices meeting (IEDM). December 7–9, 2009, Baltimore, (IEEE, 2009), pp. 1–4
  2. G. Bae, D.I. Bae, M. Kang, S.M. Hwang, S.S. Kim et al., 3nm GAA Technology Featuring Multi-bridge-channel FET for Low Power and High Performance Applications. 2018 IEEE international electron devices meeting (IEDM). 28.27.21–28.27.24 (2018). https://doi.org/10.1109/IEDM.2018.8614629
  3. S. Liao, L. Yang, T.K. Chiu, W.X. You, T.Y. Wu et al., Complementary Field-Effect Transistor (CFET) Demonstration at 48nm Gate Pitch for Future Logic Technology Scaling. 2023 International electron devices meeting (IEDM). pp. 1–4, (2023). https://doi.org/10.1109/iedm45741.2023.10413672
  4. L. Qin, C. Li, Y. Wei, G. Hu, J. Chen et al., Recent developments in negative capacitance gate-all-around field effect transistors: a review. IEEE Access 11, 14028–14042 (2023). https://doi.org/10.1109/ACCESS.2023.3243697
  5. C.-C. Yang, T.-Y. Hsieh, W.-H. Huang, C.-H. Shen, J.-M. Shieh et al., Recent progress in low-temperature-process monolithic three dimension technology. Jpn. J. Appl. Phys. 57, 04FA06 (2018). https://doi.org/10.7567/jjap.57.04fa06
  6. P. Lin, C. Li, Z. Wang, Y. Li, H. Jiang et al., Three-dimensional memristor circuits as complex neural networks. Nat. Electron. 3, 225–232 (2020). https://doi.org/10.1038/s41928-020-0397-9
  7. Q. Zhang, Y. Zhang, Y. Luo, H. Yin, New structure transistors for advanced technology node CMOS ICs. Natl. Sci. Rev. 11, nwae008 (2024). https://doi.org/10.1093/nsr/nwae008
  8. L. Liang, R. Hu, L. Yu, Toward monolithic growth integration of nanowire electronics in 3D architecture: a review. Sci. China Inf. Sci. 66, 200406 (2023). https://doi.org/10.1007/s11432-023-3774-y
  9. Q. Hua, G. Shen, Low-dimensional nanostructures for monolithic 3D-integrated flexible and stretchable electronics. Chem. Soc. Rev. 53, 1316–1353 (2024). https://doi.org/10.1039/d3cs00918a
  10. J. Goldberger, A.I. Hochbaum, R. Fan, P. Yang, Silicon vertically integrated nanowire field effect transistors. Nano Lett. 6, 973–977 (2006). https://doi.org/10.1021/nl060166j
  11. O. Shirak, O. Shtempluck, V. Kotchtakov, G. Bahir, Y.E. Yaish, High performance horizontal gate-all-around silicon nanowire field-effect transistors. Nanotechnology 23, 395202 (2012). https://doi.org/10.1088/0957-4484/23/39/395202
  12. P. Namdari, H. Daraee, A. Eatemadi, Recent advances in silicon nanowire biosensors: synthesis methods, properties, and applications. Nanoscale Res. Lett. 11, 406 (2016). https://doi.org/10.1186/s11671-016-1618-z
  13. H. Li, D. Li, H. Chen, X. Yue, K. Fan et al., Application of silicon nanowire field effect transistor (SiNW-FET) biosensor with high sensitivity. Sensors 23, 6808 (2023). https://doi.org/10.3390/s23156808
  14. C. Jia, Z. Lin, Y. Huang, X. Duan, Nanowire electronics: from nanoscale to macroscale. Chem. Rev. 119, 9074–9135 (2019). https://doi.org/10.1021/acs.chemrev.9b00164
  15. T. Arjmand, M. Legallais, T.T.T. Nguyen, P. Serre, M. Vallejo-Perez et al., Functional devices from bottom-up silicon nanowires: a review. Nanomaterials 12, 1043 (2022). https://doi.org/10.3390/nano12071043
  16. J.-H. Lee, B.-S. Kim, S.-H. Choi, Y. Jang, S.W. Hwang et al., A facile route to Si nanowire gate-all-around field effect transistors with a steep subthreshold slope. Nanoscale 5, 8968–8972 (2013). https://doi.org/10.1039/C3NR02552G
  17. B. Salem, G. Rosaz, N. Pauc, P. Gentile, P. Periwal et al., Electrical Characterisation of Horizontal and Vertical Gate-All-Around Si/SiGe Nanowires Field Effect Transistors. 2014 Silicon nanoelectronics workshop (SNW). June 8–9, 2014, Honolulu, (IEEE, 2014), pp. 1–2
  18. L. Yu, P.-J. Alet, G. Picardi, Pere Roca i Cabarrocas, An in-plane solid-liquid-solid growth mode for self-avoiding lateral silicon nanowires. Phys. Rev. Lett. 102, 125501 (2009). https://doi.org/10.1103/PhysRevLett.102.125501
  19. M. Xu, Z. Xue, L. Yu, S. Qian, Z. Fan et al., Operating principles of in-plane silicon nanowires at simple step-edges. Nanoscale 7, 5197–5202 (2015). https://doi.org/10.1039/c4nr06531j
  20. Z. Xue, M. Sun, T. Dong, Z. Tang, Y. Zhao et al., Deterministic line-shape programming of silicon nanowires for extremely stretchable springs and electronics. Nano Lett. 17, 7638–7646 (2017). https://doi.org/10.1021/acs.nanolett.7b03658
  21. S. Xu, R. Hu, J. Wang, Z. Li, J. Xu et al., Terrace-confined guided growth of high-density ultrathin silicon nanowire array for large area electronics. Nanotechnology 32, 265602 (2021). https://doi.org/10.1088/1361-6528/abf0c9
  22. W. Liao, Y. Zhang, D. Li, J. Wang, L. Yu, High-density integration of uniform sub-22 nm silicon nanowires for transparent thin film transistors on glass. Appl. Surf. Sci. 679, 161213 (2025). https://doi.org/10.1016/j.apsusc.2024.161213
  23. R. Hu, S. Xu, J. Wang, Y. Shi, J. Xu et al., Unprecedented uniform 3D growth integration of 10-layer stacked Si nanowires on tightly confined sidewall grooves. Nano Lett. 20, 7489–7497 (2020). https://doi.org/10.1021/acs.nanolett.0c02950
  24. R. Hu, Y. Liang, W. Qian, X. Gan, L. Liang et al., Ultra-confined catalytic growth integration of sub-10 nm 3D stacked silicon nanowires via a self-delimited droplet formation strategy. Small 18, e2204390 (2022). https://doi.org/10.1002/smll.202204390
  25. Y. Cheng, Z. Liu, J. Wang, J. Xu, L. Yu, Deterministic single-row-droplet catalyst formation for uniform growth integration of high-density silicon nanowires. ACS Appl. Mater. Interfaces 16, 23625 (2024). https://doi.org/10.1021/acsami.4c03991
  26. M. Radosavljevic, C.Y. Huang, W. Rachmady, S.H. Seung, N.K. Thomas et al., Opportunities in 3-D Stacked cmos Transistors. 2021 IEEE international electron devices meeting (IEDM). 34.31.31–34.31.34 (2021). https://doi.org/10.1109/iedm19574.2021.9720633
  27. V. Brouzet, B. Salem, P. Periwal, G. Rosaz, T. Baron et al., Fabrication and characterization of silicon nanowire p-i-n MOS gated diode for use as p-type tunnel FET. Appl. Phys. A 121, 1285–1290 (2015). https://doi.org/10.1007/s00339-015-9507-3
  28. S. Glassner, C. Zeiner, P. Periwal, T. Baron, E. Bertagnolli et al., Multimode silicon nanowire transistors. Nano Lett. 14, 6699–6703 (2014). https://doi.org/10.1021/nl503476t
  29. A.L. Vallett, S. Minassian, P. Kaszuba, S. Datta, J.M. Redwing et al., Fabrication and characterization of axially doped silicon nanowire tunnel field-effect transistors. Nano Lett. 10, 4813–4818 (2010). https://doi.org/10.1021/nl102239q
  30. K.E. Moselund, H. Ghoneim, M.T. Björk, H. Schmid, S. Karg et al., VLS-grown Silicon Nanowire Tunnel FET.2009 device research conference. June 22-24, 2009, University Park, (IEEE, 2009), pp. 23–24
  31. M.T. Björk, J. Knoch, H. Schmid, H. Riel, W. Riess, Silicon nanowire tunneling field-effect transistors. Appl. Phys. Lett. 92, 193504 (2008). https://doi.org/10.1063/1.2928227
  32. M. Xu, Z. Xue, J. Wang, Y. Zhao, Y. Duan et al., Heteroepitaxial writing of silicon-on-sapphire nanowires. Nano Lett. 16, 7317–7324 (2016). https://doi.org/10.1021/acs.nanolett.6b02004
  33. L. Yu, W. Chen, B. O’Donnell, G. Patriarche, S. Bouchoule et al., Growth-in-place deployment of in-plane silicon nanowires. Appl. Phys. Lett. 99, 203104 (2011). https://doi.org/10.1063/1.3659895
  34. Z. Liu, J. Yan, H. Ma, T. Hu, J. Wang et al., Ab initio design, shaping, and assembly of free-standing silicon nanoprobes. Nano Lett. 21, 2773–2779 (2021). https://doi.org/10.1021/acs.nanolett.0c04804
  35. K.W. Frese, C. Chen, Theoretical models of hot carrier effects at metal-semiconductor electrodes. J. Electrochem. Soc. 139, 3234–3243 (1992). https://doi.org/10.1149/1.2069059
  36. S.W. Chang, P.J. Sung, T.Y. Chu, D.D. Lu, C.J. Wang et al., First Demonstration of cmos Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications. 2019 IEEE International electron devices meeting (IEDM), 11.17.11–11.17.14 (2019). https://doi.org/10.1109/IEDM19573.2019.8993525
  37. F.-K. Hsueh, J.-M. Hung, S.-P. Huang, Y.-H. Huang, C.-X. Xue et al., First Demonstration of Ultrafast Laser Annealed Monolithic 3D Gate-All-Around CMOS Logic and FeFET Memory with Near-Memory-Computing macro. 2020 IEEE International electron devices meeting (IEDM). December 12–18, 2020, San Francisco, (IEEE, 2020), 40.4.1–40.4.4
  38. J. Yao, Y. Wei, S. Yang, H. Yang, G. Xu et al., Record 7(N) 7(P) Multiple VTs Demonstration on gaa si Nanosheet n/pFETs Using WFM-Less Direct Interfacial La/Al-Dipole Technique. 2022 International electron devices meeting (IEDM). December 3–7, 2022, San Francisco, (IEEE, 2022), 34.2.1–34.2.4
  39. W. Chen, L. Yu, S. Misra, Z. Fan, P. Pareige et al., Incorporation and redistribution of impurities into silicon nanowires during metal-p-assisted growth. Nat. Commun. 5, 4134 (2014). https://doi.org/10.1038/ncomms5134
  40. J.Y. Oh, J.T. Park, H.J. Jang, W.J. Cho, M.S. Islam, 3D-transistor array based on horizontally suspended silicon nano-bridges grown via a bottom-up technique. Adv. Mater. 26, 1929–1934 (2014). https://doi.org/10.1002/adma.201304245
  41. Y. Song, H. Zhou, Q. Xu, J. Niu, J. Yan et al., High-performance silicon nanowire gate-all-around nMOSFETs fabricated on bulk substrate using CMOS-compatible process. IEEE Electron Device Lett. 31, 1377–1379 (2010). https://doi.org/10.1109/LED.2010.2080256
  42. X. Zhang, J. Yao, Y. Luo, L. Cao, Y. Zheng et al., Hybrid integration of gate-all-around stacked Si nanosheet FET and Si/SiGe super-lattice FinFET to optimize 6T-SRAM for N3 node and beyond. IEEE Trans. Electron Devices 71, 1776–1783 (2024). https://doi.org/10.1109/TED.2024.3358251
  43. Y. Son, B. Frost, Y. Zhao, R.L. Peterson, Monolithic integration of high-voltage thin-film electronics on low-voltage integrated circuits using a solution process. Nat. Electron. 2, 540–548 (2019). https://doi.org/10.1038/s41928-019-0316-0
  44. Q. Li, J. Dong, D. Han, J. Wang, D. Xu et al., Back-end-of-line compatible InSnO/ZnO heterojunction thin-film transistors with high mobility and excellent stability. IEEE Electron Device Lett. 43, 1251–1254 (2022). https://doi.org/10.1109/LED.2022.3185099
  45. S. Hooda, M. Lal, C. Chun-Kuei, S.-H. Tsai, E. Zamburg et al., BEOL compatible extremely scaled bilayer ITO/IGZO channel FET with high mobility 106 cm2/V.s. 2023 7th IEEE electron devices technology & manufacturing conference (EDTM). March 7-10, 2023, Seoul, (IEEE, 2023), pp. 1–4
  46. Q. Smets, G. Arutchelvan, J. Jussot, D. Verreck, I. Asselberghs et al., Ultra-scaled MOCVD MoS2 MOSFETs with 42nm contact pitch and 250µA/µm drain current. 2019 IEEE International electron devices meeting (IEDM). December 7–11, 2019, San Francisco, (IEEE, 2019), 23.2.1–23.2.4
  47. X. Huang, C. Liu, Z. Tang, S. Zeng, L. Liu et al., High Drive and Low Leakage Current MBC FET with Channel Thickness 1.2 nm/0.6 nm. 2020 IEEE International electron devices meeting (IEDM). December 12–18, 2020, San Francisco, (IEEE, 2020), 12.1.1–12.1.4
  48. Y.Y. Chung, B.J. Chou, C.F. Hsu, W.S. Yun, M.Y. Li et al., First Demonstration of GAA Monolayer-MoS2 Nanosheet nFET with 410 μA/μm ID at 1V VD at 40 nm Gate Length. 2022 International electron devices meeting (IEDM). 34.35.31–34.35.34 (2022). https://doi.org/10.1109/IEDM45625.2022.10019563
  49. F. Wu, H. Tian, Y. Shen, Z. Hou, J. Ren et al., Vertical MoS2 transistors with sub-1-nm gate lengths. Nature 603, 259–264 (2022). https://doi.org/10.1038/s41586-021-04323-3
  50. R. Pendurthi, N.U. Sakib, M.U.K. Sadaf, Z. Zhang, Y. Sun et al., Monolithic three-dimensional integration of complementary two-dimensional field-effect transistors. Nat. Nanotechnol. 19, 970–977 (2024). https://doi.org/10.1038/s41565-024-01705-2
  51. C.-C. Yang, T.-Y. Hsieh, P.-T. Huang, K.-N. Chen, W.-C. Wu et al., Location-Controlled-Grain Technique for Monolithic 3D BEOL FinFET Circuits. 2018 IEEE International Electron Devices Meeting (IEDM). December 1–5, 2018, San Francisco. (IEEE 2018), 11.3.1–11.3.4
  52. C.-H. Chang, S.-C. Yan, C.-J. Sun, M.-Y. Huang, B.-A. Chen et al., Green Laser Crystallized poly-Si thin-film Transistor and CMOS Inverter Using HfO2-ZrO2Superlattice Gate Insulator and Microwave Annealing for BEOL Applications. 2023 Silicon Nanoelectronics Workshop (SNW). June 11-12, 2023, Kyoto, Japan. (IEEE, 2023), pp. 31–32
  53. J.-Y. Ku, J.-M. Yu, D.-H. Wang, D.-H. Jung, J.-K. Han et al., Improved SOI FinFETs performance with low-temperature deuterium annealing. IEEE Trans. Electron Devices 70, 3958–3962 (2023). https://doi.org/10.1109/TED.2023.3278626
  54. Y. Sun, W. Qian, S. Liu, T. Dong, J. Wang et al., Unexpected phosphorus doping routine of planar silicon nanowires for integrating CMOS logics. Nanoscale 13, 15031–15037 (2021). https://doi.org/10.1039/d1nr03014k
Read More
Author biographies are not available.
Download this PDF file
PDF SUPPLEMENTARY FILE
Statistic
Read Counter : 1056 Download : 782