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Vol. 17 (2025)

A Valuable and Low-Budget Process Scheme of Equivalized 1 nm Technology Node Based on 2D Materials

https://doi.org/10.1007/s40820-025-01702-7
Yang Shen
College of Integrated Circuit Science and Engineering, Shanghai Key Laboratory of Multidimensional Information Processing, East China Normal University, Shanghai 200241, People’s Republic of China
Zhejia Zhang
State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, People’s Republic of China
Zhujun Yao
Institute of Microelectronics and Beijing National Research Center for Information Science and Technology (BNRist), Tsinghua University, Beijing 100084, People’s Republic of China
Mengge Jin
College of Integrated Circuit Science and Engineering, Shanghai Key Laboratory of Multidimensional Information Processing, East China Normal University, Shanghai 200241, People’s Republic of China
Jintian Gao
Institute of Microelectronics and Beijing National Research Center for Information Science and Technology (BNRist), Tsinghua University, Beijing 100084, People’s Republic of China
Yuhan Zhao
Institute of Microelectronics and Beijing National Research Center for Information Science and Technology (BNRist), Tsinghua University, Beijing 100084, People’s Republic of China
Wenzhong Bao
State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, People’s Republic of China
Yabin Sun
College of Integrated Circuit Science and Engineering, Shanghai Key Laboratory of Multidimensional Information Processing, East China Normal University, Shanghai 200241, People’s Republic of China
He Tian
Institute of Microelectronics and Beijing National Research Center for Information Science and Technology (BNRist), Tsinghua University, Beijing 100084, People’s Republic of China

Corresponding Author: He Tian

tianhe88@tsinghua.edu.cn

Nano-Micro Letters, Vol. 17 (2025), Article Number: 191

Abstract

Emerging two-dimensional (2D) semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness. As the stacking process advances, the complexity and cost of nanosheet field-effect transistors (NSFETs) and complementary FET (CFET) continue to rise. The 1 nm technology node is going to be based on Si-CFET process according to international roadmap for devices and systems (IRDS) (2022, https://irds.ieee.org/), but not publicly confirmed, indicating that more possibilities still exist. The miniaturization advantage of 2D semiconductors motivates us to explore their potential for reducing process costs while matching the performance of next-generation nodes in terms of area, power consumption and speed. In this study, a comprehensive framework is built. A set of MoS2 NSFETs were designed and fabricated to extract the key parameters and performances. And then for benchmarking, the sizes of 2D-NSFET are scaled to a extent that both of the Si-CFET and 2D-NSFET have the same average device footprint. Under these conditions, the frequency of ultra-scaled 2D-NSFET is found to improve by 36% at a fixed power consumption. This work verifies the feasibility of replacing silicon-based CFETs of 1 nm node with 2D-NSFETs and proposes a 2D technology solution for 1 nm nodes, i.e., “2D eq 1 nm” nodes. At the same time, thanks to the lower characteristic length of 2D semiconductors, the miniaturized 2D-NSFET achieves a 28% frequency increase at a fixed power consumption. Further, developing a standard cell library, these devices obtain a similar trend in 16-bit RISC-V CPUs. This work quantifies and highlights the advantages of 2D semiconductors in advanced nodes, offering new possibilities for the application of 2D semiconductors in high-speed and low-power integrated circuits.


Highlights:
1 A set of MoS2 nanosheet field-effect transistors (NSFETs) are fabricated, with two stacking nanosheet channel, in which two parallel MoS2 channels are controlled by three gate electrodes simultaneously.
2 By building a comprehensive framework, the feasibility of replacing silicon-based complementary field-effect transistors of 1 nm node with 2D-NSFETs provides a 2D technology solution for 1 nm nodes, i.e., “2D eq 1 nm” nodes are verified.
3 The horizontally miniaturized 2D-NSFET achieves a frequency increase of 28% at a fixed power consumption and also obtains a similar trend in 16-bit RISC-V CPU.

Keywords

Two-dimensional semiconductors 1 nm technology node Nanosheet field-effect transistors Complementary field-effect transistors Horizontal scaling
Shen, Yang, Zhejia Zhang, Zhujun Yao, Mengge Jin, Jintian Gao, Yuhan Zhao, Wenzhong Bao, Yabin Sun, and He Tian. 2025. “A Valuable and Low-Budget Process Scheme of Equivalized 1 Nm Technology Node Based on 2D Materials”. Nano-Micro Letters 17 (March):191. https://doi.org/10.1007/s40820-025-01702-7.
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